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Improving performance through better partitioning of data movement in complex designs.
Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes can help engineers partition and prioritize data movement, particularly in heterogeneous designs, while still allowing them to behave as a single system.
